1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to the production of contact holes in a semiconductor device having a multi-level interconnection structure.
2. Description of the Background Art
An example of conventional methods of producing contact holes in a semiconductor memory device disclosed in Japanese Patent Application Laid-Open No. 5-75060 (1993) is illustrated in FIGS. 60 through 63. FIGS. 60 through 63 are cross-sectional views showing respective steps of the fabrication of such a semiconductor memory device. FIG. 60 is a cross-sectional view showing bit lines exposed because of misalignment in the lithographic process. FIG. 61 is a cross-sectional view showing the step of etching the bit lines and an insulative film of FIG. 60 to provide an opening of a vertical cross-sectional configuration. FIG. 62 is a cross-sectional view showing the step of removing a resist pattern shown in FIG. 61 to provide sidewalls. FIG. 63 is a cross-sectional view showing the step of providing a charge accumulation electrode, a capacitor insulative film and a plate electrode on the structure of FIG. 62.
In FIGS. 60 through 63, the reference character 1P designates a bit line; 3P designates a charge accumulation electrode; 4P designates a plate electrode; 5P designates an opening; 8P designates a first insulative film; 13P designates a field SiO.sub.2 film; 14P designates a p-type semiconductor substrate; 15P designates a capacitor insulative film serving as an insulative film when the charge accumulation electrode 3P and the plate electrode 4P form a capacitor; 16P designates a second insulative film for preventing electrical continuity between the charge accumulation electrode 3P and the bit lines 1P; 17P designates a resist pattern; and 34 designates an n.sup.+ diffusion layer.
The conventional method of producing the contact holes in the semiconductor memory device is described below with reference to FIGS. 60 through 63.
Referring to FIG. 60, a 200 nm width of the bit line 1P is shown as exposed due to misalignment in the lithographic process. First, the SiO.sub.2 films 13P are formed on the p-type semiconductor substrate 14P by the LOCOS technique as shown in FIG. 60. Then, a switching transistor and the bit lines 1P are formed. The n.sup.+ diffusion layer 34 serves as the source/drain of the switching transistor in the structure of FIG. 60. Using the resist pattern 17P as a mask, the first insulative film 8P is selectively removed by anisotropic etching to form the opening 5P therein for electrical connection between the charge accumulation electrode 3P and the n.sup.+ diffusion layer 34. During this process, the bit line 1P is exposed in the opening 5P due to mask misalignment.
With reference to FIG. 61, using the resist pattern 17P as a mask, the exposed part of the bit line 1P is etched away. Thereafter, a part of the first insulative film 8P which has been under the exposed part of the bit line 1P is etched away. The opening 5P of a vertical cross-sectional configuration is then provided.
As illustrated in FIG. 62, the resist pattern 17P is removed after the opening 5P is formed. The second insulative film 16P made of high-temperature CVD silicon oxide is deposited and then etched back by overetching to form sidewalls.
The charge accumulation electrode 3P made of polycrystalline silicon, the capacitor insulative film 15P made of silicon oxy-nitride, and the plate electrode 4P made of polycrystalline silicon are formed as shown in FIG. 63.
In the semiconductor memory device having a one-level interconnection structure, as above described, the opening 5P of the vertical cross-sectional configuration may be formed because of the step of etching the exposed part of the bit line 1P if a great width of the bit line 1P is exposed during the formation of the opening 5P, and the short-circuit between the charge accumulation electrode 3P and the bit lines 1P may be prevented because of the step of providing the second insulative film on the side surface of the opening 5P.
The contact hole forming process in the method of fabricating the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 5-75060 may prevent the short-circuit between the charge accumulation electrode 3P and the bit lines 1P when the interconnect layer includes a one-level metal interconnection.
The semiconductor memory device constructed as above described has drawbacks to be described below.
The dominating memory cell structure to which stacked storage nodes of recent dynamic RAMs are applied are a COB (capacitor over bitline) structure wherein a capacitor is provided over the bit lines 1P. When contact holes are formed in the application of the storage nodes, two interconnect layers, that is, word lines (transfer gates) and bit lines are present as a lower layer. The COB structure is a dynamic RAM cell structure wherein the stacked capacitor overlies the bit lines for structural reasons and the gate electrode immediately overlies the silicon substrate, with an insulative film therebetween, for functional reasons. The memory cells of conventionally used dynamic RAMs have been of a CUB (capacitor under bitline) construction. The CUB structure is in the form of a simple stacked capacitor (comprised of a single thin film of polycrystalline silicon) and thus is easy to process. The bit lines which are difficult-to-process metal interconnect wires are positioned as high as possible, and an interlayer insulative film is flattened. Then, the metal interconnect wires are processed over the CUB.
Recently, the COB structure wherein the capacitor is formed over the bit lines has been increasingly employed to increase the capacitor area (increase the capacitor capacitance) since advanced processing technology has enabled the metal interconnect wires to be used as the lower layer to increase the degree of freedom. The device microprocessing rules have been stricter year after year, but the need to increase the capacitor capacitance has been growing. In the CUB structure, the area of the storage nodes must be small to allow for the partial removal of the bit line contacts after the formation of the storage nodes. However, in the COB structure wherein the contact holes are not formed in the memory cells after the formation of the storage nodes, the storage nodes may be formed while making the most possible use of the minimum processing dimension rules, permitting the increase in area of the storage nodes. It has also been reported that the COB structure provides a greater (vertical) distance between the bit lines and the cell plate and a lower parasitic capacitance of the bit lines.
The method of fabricating the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 5-75060 describes the formation of the contact holes for the storage nodes without any consideration for the word lines when the two interconnect layers including the word lines and bit lines are used.
In the above described background art method, the contact holes may be formed so as to prevent the short-circuit between the charge accumulation electrode 3P and the bit lines 1P when only one metal interconnect layer including the bit lines 1P is provided since the second insulative film 16P is formed between the charge accumulation electrode 3P and the bit lines 1P. However, Japanese Patent Application Laid-Open No. 5-75060 does not disclose the semiconductor device having the two-level interconnection structure, for example, including the word lines under the bit lines, and is not simply applied to the production of the contact holes in the semiconductor device having the two-level interconnection structure. This is because simple partial removal of the word lines, like the bit lines, can result in significant losses of transistor characteristics since the width of the word lines specifies a transistor gate width.
Additionally, a great misalignment of the formed opening 5P causes the bit lines 1P to be removed in great amount to thin the bit lines 1P, resulting in disconnection and wiring resistance errors.
In this fashion, the method disclosed in Japanese Patent Application Laid-Open No. 5-75060 may be applied only to the semiconductor device having the one-level interconnection structure and presents wiring errors and wiring resistance errors of the bit lines 1P. It has therefore been desired to attain two objects: to enable the application of the method of fabricating the semiconductor device to the production of the contact holes of the semiconductor device having at least two interconnect levels, and to suppress wiring errors due to thinning of the bit lines.